1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having capacitors over a semiconductor substrate and a method of manufacturing the same.
2. Description of the Prior Art
In recent years, the semiconductor memory using the ferroelectric capacitor and the high-dielectric capacitor is regarded as the promising one. For example, the ferroelectric capacitor is formed by the steps described in the following.
First, as shown in FIG. 1A, the first metal layer 106, the PZT layer 107, and the second metal layer 108 are formed sequentially on the interlayer insulating film 104 for covering the semiconductor substrate 101. In this case, the impurity diffusion region 103 surrounded by the element isolation insulating film 102 is formed on the semiconductor substrate 101, and the conductive plug 105 is formed in the interlayer insulating film 104 on the impurity diffusion region 103.
Then, the titanium nitride layer 110 and the silicon oxide layer 111 are formed sequentially on the second metal layer 108. Then, the silicon oxide layer 111 and the titanium nitride layer 110 are patterned by the photolithography method to be left over the conductive plug 105 as the hard mask 112 having the capacitor planar shape.
Then, as shown in FIG. 1B, the second metal layer 108, the PZT layer 107, and the first metal layer 106 in the region, which is not covered with the hard mask 112, are etched sequentially. Thus, the stacked ferroelectric capacitor 113 is formed on the interlayer insulating film 104.
Then, as shown in FIG. 1C, the silicon oxide layer 111 constituting the hard mask 112 is removed, and then the titanium nitride layer 110 is removed by changing the etchant.
As described above, the reason why not the resist mask but the hard mask 112 is employed to pattern the first metal layer 106, the PZT layer 107, and the second metal layer 108 is given as follows.
That is, in order to form the stacked ferroelectric capacitor 113, if the first metal layer 106, the PZT layer 107, and the second metal layer 108 are etched successively by using the resist mask, such resist mask disappears during the etching since the resist mask has the poor etching selectivity against these layers 106, 107, 108.
Meanwhile, it is set forth in U.S. Pat. No. 6,169,009 (Patent Application Publication (KOKAI) Hei 11-354510) that the hard mask having the above double-layered structure is used to pattern the metal film and the mixed gas consisting of chlorine, oxygen, and argon is used as the etching gas. Also, it is set forth in Patent Application Publication (KOKAI) Hei 11-354510 that the SiO2 film in the hard mask disappears in the middle of the etching of the metal film.
It is preferable that the silicon oxide layer should be employed as the hard mask in patterning the PZT layer that is put between the first and second metal layers. Thus, the disappearance of the silicon oxide layer serving as the hard mask during the etching of the PZT layer causes the remarkable reduction in the etching rate of the PZT layer. Therefore, it is important to leave the silicon oxide layer 111 as the hard mask until the etching of the PZT layer is ended.
Accordingly, as shown in FIG. 1B, not only the titanium nitride layer 110 constituting the hard mask 112 but also the silicon oxide layer 111 is left on the second metal layer 108 in the state after the etching of the second metal layer 108, the PZT layer 107, and the first metal layer 106 are ended.
The silicon oxide layer 111 and the titanium nitride layer 110 are removed by the etching after the formation of the capacitor 113 is completed.
However, when the SiO2 layer 111 constituting the hard mask 112 is removed, the interlayer insulating film 104 formed of the silicon oxide is also etched around the capacitor 113. Thus, the level difference between the capacitor 113 and the periphery area is increased. If such level difference is increased, such a disadvantage is caused that the filling property of the second-layer interlayer insulating film between plural capacitors 112 becomes worse.